1. Field of the Invention
This invention relates to a semiconductor nonvolatile memory transistor structure and a method of fabricating the same, particularly to a technology for improving the memory characteristic and enhancing the reliability of a semiconductor nonvolatile memory transistor having a memory insulator film composed of a tunnel insulator film, a memory nitride film and a top oxide film and known as the MONOS (Metal Oxide Nitride Oxide Semiconductor).
2. Description of the Related Art
Data rewrite of a MONOS nonvolatile memory transistor is generally effected by applying bias voltage to the memory gate electrode to inject electrons or holes from the semiconductor substrate through the tunnel insulator film into the memory nitride film, the interface between the tunnel insulator film and the memory nitride film, and the interface between the memory nitride film and the top oxide film.
The structure of the conventional MONOS nonvolatile memory transistor will be explained with reference to the schematic sectional view of FIG. 25.
As shown in FIG. 25, a MONOS structure is configured by providing a field oxide film 2 around a memory device region on the surface of a semiconductor substrate 1 exhibiting P-type conductivity (first conductivity type), providing a tunnel insulator film 31, a memory nitride film 5 and a top oxide film 6 on the memory device region of the semiconductor substrate 1 to constitute a memory insulator film 8, and providing a memory gate electrode 9 on the memory insulator film 8.
A source 10 and a drain 11 composed of heavily doped layers exhibiting N-type conductivity (second conductivity type) are further provided on the memory device region of the semiconductor substrate 1 in self-alignment with the memory gate electrode 9.
An interlevel insulator 12 composed mainly of a silicon dioxide film is provided over the whole surface of the semiconductor substrate 1 and interconnections 14 are provided through contact holes 13 formed in the interlevel insulator 12 to contact the source 10, the drain 11 and, though not illustrated, the memory gate electrode 9.
Data rewrite of such a conventional MONOS nonvolatile memory transistor is effected by applying bias voltage to the memory gate electrode 9.
Specifically, in the case of an N-channel memory transistor, positive bias voltage is applied to the memory gate electrode 9, and the semiconductor substrate 1, the source 10 and the drain 11 are grounded to cause electrons to be injected from the semiconductor substrate 1 through the tunnel insulator film 31 into the memory insulator film 8 to be captured in the memory nitride film 5, at the interface between the tunnel insulator film 31 and the memory nitride film 5,. and at the interface between the memory nitride film 5 and the top oxide film 6.
The threshold voltage of the N-channel MONOS nonvolatile memory transistor after electron capture is higher than normal. That is, enhancement operation occurs. This is called the write state.
If, oppositely from this, the memory gate electrode 9 is grounded and positive bias voltage is applied to the semiconductor substrate 1, the source 10 and the drain 11, holes are injected from the semiconductor substrate 1 through the tunnel insulator film 31 into the memory insulator film 8 to be captured in the memory nitride film 5, at the interface between the tunnel insulator film 31 and the memory nitride film 5, and at the interface between the memory nitride film 5 and the top oxide film 6.
The threshold voltage of the N-channel MONOS nonvolatile memory transistor after hole capture is lower than normal. That is, depletion operation occurs. This is called the erase state.
Thus in the MONOS nonvolatile memory transistor, data write is effected by injecting electrons or holes from the semiconductor substrate 1 through the tunnel insulator film 31 into the memory insulator film 8 to establish the write state or the erase state.
In the case of a P-channel memory transistor, the relationship between the polarity of the bias voltage and the write state/erase state is reversed from that of the N-channel memory transistor explained above. That is, it assumes write state when holes are injected and assumes erase state when electrons are injected.
In either case, the data rewrite operation of the MONOS nonvolatile memory transistor depends heavily on the thickness, material and properties of the tunnel insulator film 31.
When the thickness of the tunnel insulator film 31 is increased, for instance, the injection efficiency of electrons and holes from the semiconductor substrate decreases. This lowers the write speed and, by decreasing the number of electrons and holes injected, reduces the number captured. Data write therefore becomes difficult.
As a result, the conventional tunnel insulator film 31 has been constituted as a silicon nitrided oxide film formed by nitridation of a silicon oxide film.
The operation of this silicon nitrided oxide film will be explained with reference to the energy band diagram shown in FIG. 26.
In the energy band diagram shown in FIG. 26, the energy state is represented vertically and the structure of the memory insulator film 8 of the MONOS nonvolatile memory transistor is represented horizontally.
This energy band diagram shows the erase operation of an N-channel MONOS nonvolatile memory transistor when positive bias voltage is applied to the semiconductor substrate 1. The film structure is represented as slanted proportionally to the bias.
When the tunnel insulator film 31 of the memory insulator film 8 is constituted as the silicon oxide film 32 represented in broken lines, the barrier height of the silicon oxide film 32 to holes from the semiconductor substrate 1 (lower side in FIG. 26) is, at about 3.8 eV, higher than the approximately 3.2 eV barrier height of the silicon oxide film 32 to electrons (upper side in FIG. 26).
As a result, the write speed on the erase side, which generally involves hole injection, is decreased when the silicon oxide film 32 is used as the tunnel insulator film 31.
Because of this, the practice is to improve the speed on the erase side by using as the tunnel insulator film 31 of the memory insulator film 8 a silicon nitrided oxide film obtained by nitridation of the silicon oxide film 32.
Specifically, use of the silicon nitrided oxide film 3 represented in solid lines in FIG. 26 in place of the silicon oxide film 32 makes the barrier height to holes from the semiconductor substrate 1 (lower side in FIG. 26) about 3.3 eV, lower than the barrier height of the silicon oxide film 32 (about 3.8 eV). As a result, the hole injection efficiency is improved and the speed of the erase operation increased.
However, since the barrier height of the tunnel insulator film 31 is also lowered from the viewpoint of holes captured in the memory nitride film 5, at the interface between the tunnel insulator film 31 and the memory nitride film 5, and at the interface between the memory nitride film 5 and the top oxide film 6, holes escape more readily to the side of the semiconductor substrate 1. This degrades the data retention characteristic.
In the case of the P-channel MONOS nonvolatile memory transistor, the speed of the write operation is increased owing to the improvement in the hole injection efficiency but the data retention characteristic is again degraded because captured holes escape readily to the side of the semiconductor substrate 1.
Thus, even in the conventional MONOS nonvolatile memory transistor, the speed of the erase operation or the write operation can be increased by adopting a silicon nitrided oxide film as the tunnel insulator film of the memory insulator film and thereby improving the injection efficiency of holes in the erase operation or the write operation.
However, use of a silicon nitrided oxide film as the tunnel insulator film lowers the barrier height of the tunnel insulator film from the viewpoint of the holes that the erase operation or the write operation causes to be captured in the memory nitride film, at the interface between the tunnel insulator film and the memory nitride film, and at the interface between the memory nitride film 5 and the top oxide film of the memory insulator film, thereby allowing the holes to escape easily to the side of the semiconductor substrate and thus degrading the data retention characteristic.